The present invention is related to the field of direct-current (DC) motor controller circuits.
Field-effect transistors (FETs) are commonly used as switches in the output stage of DC motor controllers to intermittently provide high current to windings of the motor to control the motor's rotation. In one common configuration two FETs are connected in series between a positive power supply and ground, and the node between the FETs is connected to a winding of the motor. In this configuration the FET connected between the supply and the winding is commonly referred to as the "high-side" FET, and the other as the "low-side" FET. In a multi-phase motor, other pairs of FETs are similarly connected to the other windings of the motor. Separate drive signals are provided to each FET, and the FETs are switched on and off, or commutated, in a predetermined pattern through each revolution of the motor such that the direction and speed of motor rotation are maintained in a desired fashion.
One particular type of FET used in motor drivers is a double-diffused metal-oxide-semiconductor (DMOS) FET. A DMOS FET offers similar performance per area as an N-channel MOS (NMOS) device, yet it is more suitable for high-voltage motor applications. One of the characteristics of DMOS FETs is that in addition to source, gate, and drain terminals, they have a fourth terminal connected to a "body" region of the device. In many applications the body terminal is connected directly to the source terminal. When DMOS FETs are used to drive a motor winding as described above, the low-side DMOS FET in each pair has its drain connected to the winding, and its source and body connected to ground. The high-side DMOS FET has its drain connected to the DC power supply, and its source and body connected to the winding.
When a motor driver FET switches abruptly from the conducting state to the non-conducting state, it is possible for the voltage at the node connected to the winding to momentarily take on a large value with respect to other voltages in the driver circuit. This excessive voltage is commonly referred to as either "overshoot" or "undershoot". "Overshoot" refers to an overvoltage condition in which the driver output voltage is higher than the voltage at the drain of the high-side FET, which is typically the power supply voltage. "Undershoot" refers to an undervoltage condition in which the driver output voltage is lower than the voltage at the source/body of the low-side FET, which is typically ground. Overshoot and undershoot arise from the fast switching of currents in an inductive circuit component such as a motor winding.
Inductive overshoot and undershoot voltages can cause problems for motor driver circuits. An inductive overshoot above the DC supply can turn on a parasitic vertical bipolar positive-negative-positive (PNP) transistor formed by the body and drain of the high-side DMOS FET and the P-type substrate used to fabricate the integrated circuit. The body, drain, and P-type substrate are the emitter, base and collector of the PNP transistor, respectively. If the overshoot voltage is great enough, this parasitic PNP transistor can conduct substantial current, which can lead to two problems. One problem, commonly known as "latch-up", is a condition in an integrated circuit in which a parasitic silicon-controlled rectifier becomes permanently turned on, and it conducts such an extremely high current that the integrated circuit is destroyed. Another problem with current flowing through the parasitic PNP transistor is that current is being diverted away from an intended current path between the body and drain of the FET (i.e., the motor winding and the DC supply), resulting in wasted power. This waste can be especially problematic under power-loss conditions when the motor driver circuitry is being powered by the back electromagnetic force (back EMF) of the motor windings.
An inductive undershoot voltage less than ground can turn on a parasitic PN diode formed by the P.sup.- -type substrate and the N.sup.+ -type drain of the low-side DMOS FET. If this diode becomes forward biased, it injects minority carriers into the substrate, which could potentially lead to latchup problems as previously described.
One general approach to preventing the parasitic PNP transistor or PN diode from conducting is to regulate the driver output voltage so that it is prevented from reaching a value effective to turn the devices on. One common manner of regulating the output voltage is to connect Schottky diodes in parallel with the driver FETs. A Schottky diode becomes forward biased at a lower voltage than a regular PN junction diode. The Schottky diode in parallel with the high-side FET conducts when the output voltage becomes higher than the supply voltage by the voltage drop of a forward-biased Schottky diode. Similarly, the Schottky diode in parallel with the low-side FET conducts when the output voltage becomes lower than ground by the voltage drop of a forward-biased Schottky diode. The conducting of the Schottky diodes prevents the output voltage from reaching a value high or low enough to cause the parasitic devices in either the high-side or low-side FET to conduct.
The use of Schottky diodes increases the number of components used for the motor controller circuitry, and therefore increases the cost of the circuitry and the amount of circuit board space needed by the circuitry. These increases are significant in a motor controller circuit that is contained on a single integrated circuit or chip. The use of off-chip components such as Schottky diodes reduces the benefits associated with integrated circuits, such as reduced cost and reduced space requirements.
Another approach to the problem of excessive overshoot specifically is to manufacture the driver FETs by a process that is designed to minimize the effect of the parasitic PNP transistor. In one such process, a layer of N.sup.+ semiconductor is created within the silicon substrate at the site where a DMOS FET is to be created. This "buried" N.sup.+ layer creates a barrier to the flow of current between the body of the FET (PNP emitter) and the substrate (PNP collector). As a result, the output voltage need not be regulated to avoid turning on the parasitic PNP transistor. Instead, the buried layer limits the amount of current conducted by the parasitic PNP transistor to a small fraction of the current conducted between the body and drain of the FET.
Unfortunately, an N.sup.+ buried layer does not help in the case of an undershoot which turns on the drain-to-substrate parasitic PN diode. Also, the use of buried layers requires a specialized semiconductor manufacturing process that is more complicated and expensive than is otherwise necessary for the manufacture of motor driver circuits. Accordingly, there has been a need for alternative solutions to the problem of excessive overshoot and undershoot on the output of motor driver FETs that allows for the use of relatively simple semiconductor processing techniques and that enables the cost and size advantages of circuit integration to be fully realized.